1. Field of the Invention
The invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to a configurable input/output (I/O) buffer for an FPGA.
2. Description of the Background Art
Existing I/O structures for integrated circuits (ICs) are typically designed to function according to a specific I/O standard. There are several different I/O standards in use, and new standards are often introduced. These I/O standards typically include such factors as output drive strength, receiver type, output driver type, and output signal slew rate. One such I/O standard is the GTL+ standard, described in pages 46 through 50 of the Pentium Pro Processor data sheet entitled "PENTIUM PRO PROCESSOR AT 150 MHz, 166 MHz, 180 MHz and 200 Mhz", published November 1995 and available from Intel Corporation, 2200 Mission College Blvd., Santa Clara, Calif. 95052-8119, which are incorporated herein by reference. ("Pentium" is a registered trademark owned by Intel Corporation.)
A typical Input/Output Block (IOB) in an FPGA supports only one I/O standard. However, FPGAs are often used to implement "glue logic" (logic used to interface between two or more standard circuits) and therefore often interface with multiple ICs. It would be desirable for an FPGA to be able to interface with ICs that follow two or more different I/O standards.
Additionally, existing I/O structures are typically designed to function at a specific supply voltage. For example, for many years, the majority of commercially available ICs were designed to function at a supply voltage of 5 Volts. However, as the typical gate length decreases throughout the IC industry, the typical supply voltage used in FPGAs and other ICs is decreasing. Many ICs are now available that function at 3.3 Volts, and voltages of 2.5 Volts and below are commonly discussed. Therefore, it would be desirable for an FPGA to be able to interface with different ICs that function at two or more different supply voltages.
It is known in FPGA design to use one voltage for driving outputs and a different voltage in the interior (core) of the FPGA. One FPGA having a separate output voltage supply is the FLEX 10K.TM. FPGA from Altera Corporation, as disclosed on pages 54 to 59 of the "FLEX 10K Embedded Programmable Logic Family Data Sheet" from the Altera Digital Library 1996, available from Altera Corporation, 2610 Orchard Parkway, San Jose, Calif. 95134-2020, which are incorporated herein by reference. ("FLEX 10K" is a trademark of Altera Corporation.) In the FLEX 10K device, output voltage supply pins are provided that can be connected as a group to only one output supply voltage, either a 3.3-Volt or a 5-Volt power supply. Known FPGAs therefore typically provide for a single output supply voltage, which applies to all configurable I/O buffers on the FPGA.
Output slew rate is also programmable in known FPGAs including the XC3000 family of devices from Xilinx, Inc., as described on pages 4-292 through 4-293 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) However, in such FPGAs, factors such as output drive strength, receiver type, and output driver type are not known to be configurable to meet a particular I/O standard.
Some I/O standards require that an input reference voltage be supplied. An input voltage above the input reference voltage is interpreted as a "high" voltage level; an input voltage below the input reference voltage is interpreted as a "low" voltage level. Therefore, the input reference voltage establishes a "trip point" for interpreting input signals. As far as is known, no FPGA allows a user to supply an input reference voltage.